In the printed circuit board assembly process, wherein many components are soldered down, a method for continuity testing was devised to isolate defects on the board to enhance yields and lower the costs. In this test mode, the individual outputs of a component are preset to known states, and corresponding inputs are detected for these states. Defects such as opens or shorts to voltage supply or adjacent lines are detected with the patterns received. This testing is done at a sufficiently low frequency where signal integrity is not an issue. This method, known as JTAG boundary scan, has been adopted as an industry standard as IEEE 1149.1 and also IEEE 1149.4.
In a high-speed PC board assembly, the fastest signals are typically AC-coupled through series capacitors, enabling components with different technologies and supply voltages to be interfaced. As the boundary scan standard was not designed for AC connected signals, these signals are not testable with IEEE 1149.1.
Recently, the number of AC-coupled signals has increased dramatically and defects on these untestable signal paths have greatly impacted board yields. Thus, a method of boundary scan testing for these AC-coupled data paths needs to be developed to address this problem.
AC-coupled high-speed signal paths are increasingly transmitted as differential pairs to maximize signal integrity. This has the undesirable effect of masking many common defects, such as open solder joints. Masking occurs when a defect in one leg of a differential pair does not prevent information from being transmitted on the other at lower speeds. However, the high frequency performance of this path is unacceptably degraded.
The boundary scan testing methodology allows Inputs and Outputs ports of an IC to be isolated from the internal core logic, and allows these ports to be observed and controlled during the boundary scan tests via registers. The values of the registers of the output ports are sequentially loaded and set to a known state. The values of the registers of the input ports are read sequentially, and are compared to their expected values by the tester. A test clock is used to toggle the states of these registers in and out of the chip under test.
The present invention is boundary scan testing methods that detect manufacturing defects in differential pairs. Boundary scan testing methods that detect manufacturing defects in differential pairs may be based on a selected signal parameter: phase or frequency. The data is encoded by the signal parameter. In one variation, the signal parameter is compared to reference parameter data provided by the transmitter. In a second variation, the reference parameter data is sent or derived from an external source. All the components on board are synchronized with this external source. In a third variation, the reference parameter data is embedded in each AC signal between the transmitter and receiver. Two lines of one differential link are used to send different patterns.
In a first embodiment of a timing-based solution, the data is encoded into phase information of a repetitive pulse signal of 50% duty cycle. A logic xe2x80x9c1xe2x80x9d can be encoded as a 0xc2x0 phase-shifted pulse and a logic xe2x80x9c0xe2x80x9d can be encoded as a 180xc2x0 phase-shifted pulse. The pulse frequency needs to be high enough to pass through the AC coupling capacitors. To receive and detect exact phase information, the receiver (RX) needs to have reference phase information.
The second embodiment of a timing-based solution identifies multiple reference sources in one transmission. The reference phase information is sent from an external source. All the components on board are synchronized with this external source. The phase-shifted pulses can be generated according to this external source and also can be detected using the same external source. Multiple chip connections can be handled, as there is one global reference. However, an external global reference generator and one additional pin to each component are required.
The third embodiment of the timing-based solution also identifies multiple reference sources in one transmission. The reference phase information is embedded in each AC signal. Two lines of one differential link are used to send different patterns. Each line refers to the other line as a reference. In the receiver side, one line can recover the data using the other line as a clock and vice versa. The global reference is eliminated and each differential link is treated independently. However, this method requires two lines for proper testing.
The frequency-based solution of the present invention uses different frequencies instead of different phases of an AC signal. The logic xe2x80x9c1xe2x80x9d can be converted to f1 frequency signal and data zero may be converted to f0 frequency signal; both f1 and f0 frequency signals are ideally 50% duty cycle. On the receiver side, a frequency detector can detect the frequency of received signals. In general, a frequency detector needs a reference frequency to know whether the received frequency is higher or lower than the reference. So, in a frequency-based solution, a reference frequency is needed.
In a generic frequency-based solution, a transmitter output driver and a receiver input buffer are interposed by a pair of coupling capacitors. A frequency encoder provides input to the transmitter. A frequency generator receives a global source frequency, fg and generates a high frequency corresponding to a logic HIGH f1, a low frequency corresponding to a data ZERO f0, and a reference frequency fREF. During test, the frequency encoder receives the high and low frequencies and the incoming data. The incoming data is mapped into signals of high and low frequencies and then applied to the transmitter. At the receiver, these signals are compared to a reference frequency, and are decoded back to the initial datastream.
In a first embodiment of the frequency-based embodiment, the reference frequency is sent from the transmitter side. The received reference frequency is used to detect the received signal frequency on the receiver side. However, similar to the first embodiment of the time-based solution, when multiple reference sources are in the transmission is difficult to determine which one is the exact reference.
In a second embodiment of the frequency-based solution, the reference frequency can be sent or derived from an external source clock. All the components on board have the same reference frequency to detect the received signal. The frequency detector uses this reference frequency to decide the frequency of the received signal. This embodiment is the frequency corollary to the second embodiment of the timing-based solution.
In the third embodiment of the frequency-based solution, the reference frequency information can be embedded in each link. The two different frequencies can be sent through two lines in one differential link. On the receiver side, one line""s frequency detector uses the other line""s received signal as a reference frequency and vice versa. This embodiment is the frequency corollary to the third embodiment of the timing-based solution.